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| author | Adam Joseph <adam@westernsemico.com> | 2022-10-26T09·22-0700 |
|---|---|---|
| committer | Adam Joseph <adam@westernsemico.com> | 2022-10-28T02·57+0000 |
| commit | a79bbad03b370e362e72a8ea616627c2aebd6d48 (patch) | |
| tree | 6ee3e67e1c098fa206b02bf410a3bb3765983552 /tvix/eval/src/value/attrs.rs | |
| parent | aa4191a44c6448b8986b743b6f3ec4c10f835f79 (diff) | |
docs(tvix/eval): add "intern literals" to future optimisations r/5217
Signed-off-by: Adam Joseph <adam@westernsemico.com> Change-Id: I460230863de853ca5248733bc977d4780b216f36 Reviewed-on: https://cl.tvl.fyi/c/depot/+/7096 Tested-by: BuildkiteCI Reviewed-by: sterni <sternenseemann@systemli.org>
Diffstat (limited to 'tvix/eval/src/value/attrs.rs')
0 files changed, 0 insertions, 0 deletions